https://scholars.lib.ntu.edu.tw/handle/123456789/174734
標題: | 考慮光罩效應之積體電路擺置規劃系統 Lithography Friendly Multilevel Analytical Placement |
作者: | 趙文綺 Chao, Wen-Chi |
關鍵字: | 置放;微影;多層次;解析式;光學鄰近校正技術;可製造性;placemet;lithography;multilevel;analytical;OPC;manufacturability | 公開日期: | 2009 | 摘要: | 由於次波長微影技術, 製成需要仰賴密集地使用解析度增強技術Resolution-Enhancement Techniques, RETs),其中光學鄰近校正技術Optical Proximity Correction, OPC) 最常被工業界用來增強可製造性。此外,慮可製造性的實體設計更成為設計流程中輔助增強可製造性的主流。本篇論文中,我們提出了第一個考慮光學鄰近校正技術下幫助微影的多層解析式置放。我們先根據光學鄰近校正技術後的微影模擬結果,建立一個元件元件造成的微影代價計算模型,接著利用這個模型來引導置放。根據多層次解式的置放架構,我們提出了兩個估計微影代價的方法來引導初期置放,接著在法化階段中考慮微影代價,最後在細部置放階段同時最佳化微影代價和線長。們利用ISCAS[2] 和ISPD04[1] 電路來做測試。光是靠我們的細部置放算法,就可以讓兩組測試電路分別降低平均12.73% 和 36.86% 的微影代價。較於先前所提出的演算法中效果最好的多列最佳化演算法[12],我們所提出演算法更進一步增進了11.08% 和 34.01% 的可製造性。為了觀察每個階段的效,我們引用了不同的流程來做驗證。而從實驗結果我們可以看出各個階段對彼此有正面的影響。相較於只考慮線長的NTUplace3[6],完整的幫助微影置可以分別對ISCAS 和ISPD04 測試電路減少26.98% 和50.94% 的微影代價,並且只增加不到3% 的線長。這個結果顯示我們的作法可以在幾乎相同的線長品質顯著的增進可製造性,並且達到比所有先前演算法所得到的結果都要好的效。 Due to the sub-wavelength lithography, manufacturing requires intensive use ofesolution-Enhancement Techniques (RETs), among which Optical Proximity Cor-ection (OPC) is the most popular technique in industry, to improve printability.oreover, physical design for manufacturability becomes the major trend in theesign flow to assist the success of manufacturing.n this thesis, we propose the first lithography friendly multilevel analyt-cal placement considering OPC. We first generate a cell-to-cell lithography costodel based on post-OPC lithography simulation, and then use this model to guideur placement. Based on the multilevel analytical placement framework, we use probability-based cost estimation model for the clustering process, and a ratio-ased cost estimation model for the spreading process, to estimate lithography cost.he clustering and spreading processes are adjusted by our cost estimation models.ith the information provided by our model, our global placement is able to gen-rate a low lithography cost result for the next stage. Then legalization aligns cells to nearby rows considering lithography cost. Finally, detailed placement simultane-usly optimizes lithography cost and wirelength.e test our approach on ISCAS benchmark circuits [2] and ISPD04 IBMenchmark circuits [1]. Based on the experimental results, our lithography friendlyetailed placement alone can already achieve 15.06% and 36.86% lithography costeduction. The results are 13.94% and 34.01% better on printability than the pre-iously proposed detailed placement algorithm-Multiple-Row Optimization Algo-ithm [12], which is the most effective algorithm in the literature. To examine theffectiveness of our approach, we apply different placement flows and compare theesults with the un-lithography-aware wirelength-driven NTUplace3 [6]. The effec-iveness of each stage and the positive impacts between different stages are observedrom the results. By applying the complete flow (which has the highest quality onrintability) of our lithography friendly placement, we can achieves 20.86% and0.94% lithography cost reduction on ISCAS benchmark circuits [2] and ISPD04BM benchmark circuits [1], respectively, comparing with wirelength-driven NTU-lace3, with only less than 3% wirelength overhead. The results show that ourpproach can effectively achieve significant improvements on printability, which hashe best results among all the related works, without notable wirelength qualityecrease. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/189257 |
顯示於: | 電子工程學研究所 |
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ntu-98-R96943109-1.pdf | 23.32 kB | Adobe PDF | 檢視/開啟 |
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