https://scholars.lib.ntu.edu.tw/handle/123456789/174759
標題: | 利用自動分割於分散式平行驗證模擬 Automatic Partitioner for Distributed Parallel Verification Simulation |
作者: | 康哲彥 Kang, Jeh-Yen |
關鍵字: | 分散式模擬;平行式模擬;暫存器層次分割;行為層次分割;Distributed Simulation;Parallel Simulation;RTL Level Partitioner;Behavior Level Partitioner | 公開日期: | 2008 | 摘要: | 由於目前電路設計的複雜性越來越大,模擬驗證變成是電路發展設計上一項瓶頸,分散式平行模擬似乎是解決這問題的方法之ㄧ,為了能夠分散模擬各個行程的工作量,在過去大部分是著重邏輯層級(GATE-LEVEL)的分割,而目前我們除了做好之前的邏輯層級(GATE-LEVEL)的分割,且延伸支援暫存器層級及行為層級(RTL/Behavior)的分割模式,這個技術可以切割一些比較特別的資料結構,像是階層式變數存取(Global Access), 函式的呼叫(Function Calls)和記憶體變數的存取(Memory Access),皆都描述在本篇論文中,而這個實驗性出來的結果的確可以證明這種切割的方式,的確可以加速模擬速度 Due to the increasing complexity of circuit design, the verification through simulation has become a bottleneck of the IC design process. Distributed parallel simulation seems to be one of the best ways to solve the problem. In order to distribute the workload of the simulation into multiple processes, the design has to be carefully partitioned first. Most previous technique had focused on gate level partition. At present, we work extends a previously implemented Verilog gate-level partitioner to support RTL and behavior level partitioning. This technique can be used for partitioning special information structure, such as global access, function calls and memory access which are described in this paper. The experimental results show that our techniques are capable of accelerating the speed of the simulation |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/189282 |
顯示於: | 電子工程學研究所 |
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