https://scholars.lib.ntu.edu.tw/handle/123456789/294631
標題: | A Low-Power Digital Matched Filter for Direct-Sequence Spread Spectrum Signal Acquisition | 作者: | M. L. Liou TZI-DAR CHIUEH |
關鍵字: | Digital matched filter; Double edge trigger; Gated pullup; High rate compressor; Prefiltering structure; Spread spectrum | 公開日期: | 六月-2001 | 卷: | 36 | 期: | 6 | 起(迄)頁: | 933-943 | 來源出版物: | IEEE Journal of Solid-State Circuits | 摘要: | This paper presents a low-power 128-tap dual-channel direct-sequence spread-spectrum (DSSS) digital matched-filter chip. Design techniques used to reduce the power consumption of the system include latch-based register file filter structure, a high-rate compression scheme, optimized compressor cells, and semicustom layout design. To further reduce the power consumption and the hardware requirement of the clock tree, a double-edge-triggered clocking scheme is adopted. The proposed chip is fabricated using a 0.8-μm standard CMOS process. As the experimental results of the chip indicate, the matched filter can operate at 50 MHz and dissipates 184 mW at 5-V supply voltage. The supply voltage can be scaled down to 2 V for lower speed applications. As a consequence, the proposed design has low power consumption and can be used for code acquisition of DSSS signals in portable systems. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/294631 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0035368242&doi=10.1109%2f4.924856&partnerID=40&md5=912f5b4f68554903e8fdcdc204a20577 |
ISSN: | 00189200 | DOI: | 10.1109/4.924856 | SDG/關鍵字: | Code acquisition; Digital matched filter; Double edge trigger; CMOS integrated circuits; Direct sequence systems; Electric power supplies to apparatus; Integrated circuit layout; Signal detection; Digital filters |
顯示於: | 電機工程學系 |
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