DC 欄位 | 值 | 語言 |
dc.contributor | Dept. of Electr. Eng., National Taiwan Univ. | en |
dc.contributor.author | Cheng, C.-C. | en_US |
dc.contributor.author | Huang, C.-T. | en_US |
dc.contributor.author | Tseng, P.-C. | en_US |
dc.contributor.author | Pan, C.-H. | en_US |
dc.contributor.author | LIANG-GEE CHEN | en_US |
dc.creator | Cheng, C.-C.;Huang, C.-T.;Tseng, P.-C.;Pan, C.-H.;Chen, L.-G. | - |
dc.date.accessioned | 2018-09-10T05:15:46Z | - |
dc.date.available | 2018-09-10T05:15:46Z | - |
dc.date.issued | 2005 | - |
dc.identifier.issn | 02714310 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33947638761&doi=10.1109%2fISCAS.2005.1465804&partnerID=40&md5=eee8316f833e5874df472f0386952e2f | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/313902 | - |
dc.description.abstract | In this paper, a memory-efficient VLSI implementation for line-based 2-D DWT, named multiple-lifting scheme, is proposed.Memory bandwidth and memory size dominate the cost of 2-D DWT and are highly related to the total power and area of 2-D DWT VLSI implementation, respectively. The proposed multiple-lifting scheme can reduce not only the average memory bandwidth but about 50% area of line buffer in 2-D DWT module. The corresponding data scan, M-scan, is proposed to achieve the multiple-lifting scheme and eliminate the data buffer as well. © 2005 IEEE. | - |
dc.format | application/pdf | en |
dc.format.extent | 189469 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en | en |
dc.relation | Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on | en |
dc.relation.ispartof | Proceedings - IEEE International Symposium on Circuits and Systems | - |
dc.source | AH | - |
dc.subject.other | Data buffers; Lifting schemes; Memory bandwidths; Memory size; Total power; VLSI implementation; Discrete wavelet transforms | - |
dc.title | Multiple-lifting Scheme: Memory-efficient VLSI implementation for line-based 2-D DWT | - |
dc.type | conference paper | en |
dc.relation.conference | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 | - |
dc.identifier.doi | 10.1109/ISCAS.2005.1465804 | - |
dc.identifier.scopus | 2-s2.0-33947638761 | - |
dc.relation.pages | 5190-5193 | - |
item.cerifentitytype | Publications | - |
item.fulltext | with fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.openairetype | conference paper | - |
item.grantfulltext | open | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.orcid | 0000-0001-9746-9355 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系
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