https://scholars.lib.ntu.edu.tw/handle/123456789/316479
標題: | SoC test scheduling using the B*-tree based floorplanning technique | 作者: | Wuu, J.-Y. Chen, T.-C. YAO-WEN CHANG |
公開日期: | 2005 | 卷: | 2 | 起(迄)頁: | 1188-1191 | 來源出版物: | Asia and South Pacific Design Automation Conference, ASP-DAC | 摘要: | We present in this paper a new algorithm to co-optimize the problems of test scheduling and core wrapper design under power constraints for core-based SoC (System on Chip) designs. The problem of test scheduling is first transformed into a floorplanning problem with a given maximum height (test access mechanism width) constraint. Then, we apply the B*-tree based floorplanning technique to solve the SoC test scheduling problem. Experimental results based on the 1TC02 benchmarks show that our method is very effective and efficient-our method obtains the besr results ever reported for SoC test scheduling with power constraint in every efficient running time. Compared with recent works, our method achieves average improvements of 4.7% to 20.1%. © 2005 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-34547364038&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/316479 |
SDG/關鍵字: | Computer aided design; Programmable logic controllers; Scheduling; System-on-chip; Testing; Core wrapper designs; Floor-planning; Power constraints; Running time; SOC (system on chip); Soc test scheduling; Test access mechanism; Test scheduling; Integrated circuit design |
顯示於: | 電子工程學研究所 |
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