https://scholars.lib.ntu.edu.tw/handle/123456789/316493
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wong, D.F. | en_US |
dc.contributor.author | Wong, C.K. | en_US |
dc.contributor.author | YAO-WEN CHANG | - |
dc.creator | Chang, Yao-Wen;Wong, D.F.;Wong, C.K. | - |
dc.date.accessioned | 2018-09-10T05:23:30Z | - |
dc.date.available | 2018-09-10T05:23:30Z | - |
dc.date.issued | 1995 | - |
dc.identifier.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-0029500697&partnerID=MN8TOARS | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/316493 | - |
dc.description.abstract | Unlike traditional ASIC routing, the feasibility of routing in FPGA's is constrained not only by the available space within a routing region, but also by the routing capacity of a switch block. Recent work [6] has established the switch-block capacity as a superior congestion-control metric for FPGA global routing. However, the work has two deficiencies: (1) its algorithm for computing the switch-block capacity is not efficient, and (2) it, as well as the other recent works [1, 4, 14], only modeled one type of routing segments-single-length lines. To remedy the deficiencies, we present in this paper efficient algorithms for obtaining the switch-block capacity and a graph modeling for routing on the new-generation FPGA's with a versatile set of segment lengths. Experiments show that our algorithms dramatically reduce the run times for obtaining the switch-block capacities. Experiments with a global router based on the switch-block and channel densities for congestion control show a significant improvement in the area performance, compared with one based on the traditional congestion metric. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE International Conference on Computer Design: VLSI in Computers and Processors | en_US |
dc.source | AH-Scopus to ORCID | - |
dc.subject.other | Algorithms; Application specific integrated circuits; Graph theory; Logic design; Logic gates; Mathematical models; Switching networks; Channel density; Congestion-control metric; Field-programmable gate arrays; Global routing; Graph modeling; Routing capacity; Run times; Switched-block capacity; Logic circuits | - |
dc.title | FPGA global routing based on a new congestion metric | - |
dc.type | conference paper | en |
dc.identifier.scopus | 2-s2.0-0029500697 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
dc.relation.pages | 372-378 | - |
item.fulltext | no fulltext | - |
item.openairetype | conference paper | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Information and Electronics Technologies | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-0564-5719 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電子工程學研究所 |
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