https://scholars.lib.ntu.edu.tw/handle/123456789/325750
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | JIUN-LANG HUANG | en_US |
dc.creator | J.-L. Huang | - |
dc.date.accessioned | 2018-09-10T06:03:13Z | - |
dc.date.available | 2018-09-10T06:03:13Z | - |
dc.date.issued | 2006-12 | - |
dc.identifier.issn | 09238174 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/325750 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33846682693&doi=10.1007%2fs10836-006-9444-3&partnerID=40&md5=b96497a1e7a6f7cff289091249e5827e | - |
dc.description.abstract | An on-chip RMS jitter testing technique for design-for-test (DfT) applications is presented in this paper. In addition to utilizing a less complicated low tap-count variable delay line to sample the jitter's cumulative density function (CDF), a sophisticated post-processing algorithm is developed to enhance process variation tolerance. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line value deviations. © Springer Science + Business Media, LLC 2006. | - |
dc.format | application/pdf | en |
dc.format.extent | 429463 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en | en |
dc.relation | Journal of Electronic Testing 22 (4-6): 387-398 | en |
dc.relation.ispartof | Journal of Electronic Testing: Theory and Applications (JETTA) | - |
dc.source | AH-anncc | - |
dc.subject | Analog/mixed-signal testing; Design-for-test; Jitter measurement; Random jitter | - |
dc.subject.other | Computer simulation; Design for testability; Electric delay lines; Microprocessor chips; Probability; Probability density function; Analog/mixed signal testing; Delay line value deviations; Jitter measurement; Random jitters; Jitter | - |
dc.title | On-chip random jitter testing using low tap-count coarse delay lines | - |
dc.type | journal article | en |
dc.identifier.doi | 10.1007/s10836-006-9444-3 | - |
dc.identifier.scopus | 2-s2.0-33846682693 | - |
dc.identifier.isi | WOS:000243407600009 | - |
dc.relation.pages | 387 - 398 | - |
dc.relation.journalvolume | 22 | - |
dc.relation.journalissue | 4-6 | - |
item.fulltext | with fulltext | - |
item.cerifentitytype | Publications | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.grantfulltext | open | - |
item.openairetype | journal article | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Program in Integrated Circuit Design and Automation | - |
crisitem.author.orcid | 0000-0002-9425-3855 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Graduate School of Advanced Technology | - |
顯示於: | 電子工程學研究所 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。