https://scholars.lib.ntu.edu.tw/handle/123456789/333719
標題: | A 62.5-625MHz anti-reset all-digital delay-locked loop | 作者: | Shao-Ku Kao Bo-Jiun Chen SHEN-IUAN LIU |
公開日期: | 七月-2007 | 卷: | 54 | 期: | 7 | 起(迄)頁: | 566-570 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks. © 2007, IEEE. All Rights Reserved. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/333719 https://www.scopus.com/inward/record.uri?eid=2-s2.0-34547583530&doi=10.1109%2fTCSII.2007.895326&partnerID=40&md5=6b3bc6e1524e4298e1b7d5365caa1081 |
ISSN: | 15497747 | DOI: | 10.1109/tcsii.2007.895326 | SDG/關鍵字: | Closed loop control systems; Detector circuits; Feedback control; Synchronization; Delay-locked loop; Dynamic frequency detector; Frequency range; Time-to-digital converter; Delay circuits |
顯示於: | 電機工程學系 |
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