https://scholars.lib.ntu.edu.tw/handle/123456789/349159
標題: | A predictive shutdown technique for GPU shader processors | 作者: | CHIA-LIN YANG Wang, Po-Han Chen, Yen-Ming Yang, Chia-Lin Cheng, Yu-Jung CHIA-LIN YANG |
關鍵字: | GPU; Leakage; Power gating | 公開日期: | 2009 | 卷: | 8 | 期: | 1 | 起(迄)頁: | 9-12 | 來源出版物: | IEEE Computer Architecture Letters | 摘要: | As technology continues to shrink, reducing leakage is critical to achieve energy efficiency. Previous works on low-power GPU (Graphics Processing Unit) focus on techniques for dynamic power reduction, such as DVFS (Dynamic Voltage/Frequency Scaling) and clock gating. In this paper, we explore the potential of adopting architecturelevel power gating techniques for leakage reduction on GPU. In particular, we focus on the most power-hungry components, shader processors. We observe that, due to different scene complexity, the required shader resources to satisfy the target frame rate actually vary across frames. Therefore, we propose the Predictive Shader Shutdown technique to exploit workload variation across frames for leakage reduction on shader processors. The experimental results show that Predictive Shader Shutdown achieves up to 46% leakage reduction on shader processors with negligible performance degradation. © 2006 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-67650602178&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/349159 |
DOI: | 10.1109/L-CA.2009.1 | SDG/關鍵字: | Clock gating; Dynamic power reduction; Dynamic voltage/frequency scaling; Frame rate; GPU; Graphics Processing Unit; Leakage; Leakage reduction; Low Power; Performance degradation; Power gating; Scene complexity; Shut-down techniques; Workload variation; Energy efficiency |
顯示於: | 資訊工程學系 |
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