https://scholars.lib.ntu.edu.tw/handle/123456789/350365
標題: | Analog placement based on symmetry-island formulation | 作者: | Lin, P.-H. Lin, S.-C. YAO-WEN CHANG |
關鍵字: | Analog circuit; Floorplanning; Physical design; Placement | 公開日期: | 2009 | 卷: | 28 | 期: | 6 | 起(迄)頁: | 791-804 | 來源出版物: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 摘要: | To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible (ASF) B*-trees to directly model the placement of a symmetry island. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*-tree or an HB*-tree is the same as that for a plain B*-tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement. © 2009 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-66549096229&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/350365 |
ISSN: | 02780070 | DOI: | 10.1109/TCAD.2009.2017433 | SDG/關鍵字: | Circuit sensitivity; Close proximity; Directly model; Electrical property; Floorplan; Floorplanning; Nonsymmetric; Packing algorithms; Physical design; Placement; Process Variation; Run-time efficiency; Search spaces; Symmetry constraints; Symmetry groups; Cost functions; Electric properties; Hysteresis motors; Integrated circuit manufacture; Quantum theory; Sensitivity analysis; Analog circuits |
顯示於: | 電子工程學研究所 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。