https://scholars.lib.ntu.edu.tw/handle/123456789/352067
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jian-Hao Lu | en_US |
dc.contributor.author | Ke-Hou Chen | en_US |
dc.contributor.author | SHEN-IUAN LIU | - |
dc.creator | Jian-Hao Lu;Ke-Hou Chen;Shen-Iuan Liu | - |
dc.date.accessioned | 2018-09-10T07:41:57Z | - |
dc.date.available | 2018-09-10T07:41:57Z | - |
dc.date.issued | 2009-02 | - |
dc.identifier.issn | 15497747 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/352067 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-62749193828&doi=10.1109%2fTCSII.2008.2010177&partnerID=40&md5=4423257c8b7e0225349d5e8ca16b932a | - |
dc.description.abstract | A 10-Gb/s low-power analog equalizer for a 10-m coaxial cable has been realized in 0.13-μm CMOS technology. To compensate the cable loss of 20 dB at 5 GHz, this equalizer with an interleaved active feedback topology is proposed without using inductors. Moreover, additional capacitive and resistive source degenerations are incorporated to meet low-frequency losses. This circuit consumes only 14 mW (excluding the output buffer) from a 1.2-V supply with the output swing up to 400 mVpp, and it occupies 0.38 × 0.34 mm2. For 8-, 9-, and 10-Gb/s pseudorandom binary sequences (PRBSs) of 231 - 1, the measured maximum peak-to-peak jitters are 26, 34, and 40 ps, respectively, and the measured bit error rate (BER) is less than 10-12. © 2009 IEEE. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems II: Express Briefs | en_US |
dc.source | AH-anncc | - |
dc.subject | Active feedback; CMOS; Equalizer; Inductorless | - |
dc.subject.other | Binary sequences; Bit error rate; Cables; CMOS integrated circuits; Electric inductors; Equalizers; Topology; Active feedback; Active feedback topology; Analog equalizers; CMOS technology; Inductorless; Output Buffer; Pseudo-random binary sequences; Source degeneration; Feedback | - |
dc.title | A 10Gb/s inductorless CMOS analog equalizer with interleaved active feedback topology | - |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TCSII.2008.2010177 | - |
dc.identifier.scopus | 2-s2.0-62749193828 | - |
dc.identifier.isi | WOS:000263919400002 | - |
dc.relation.pages | 97-101 | - |
dc.relation.journalvolume | 56 | - |
dc.relation.journalissue | 2 | - |
item.fulltext | no fulltext | - |
item.openairetype | journal article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-3765-2948 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電機工程學系 |
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