https://scholars.lib.ntu.edu.tw/handle/123456789/359369
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jie-Hong R. Jiang | en_US |
dc.contributor.author | Chih-Chun Lee | en_US |
dc.contributor.author | Alan Mishchenko | en_US |
dc.contributor.author | CHUNG-YANG HUANG | en_US |
dc.contributor.author | JIE-HONG JIANG | en_US |
dc.date.accessioned | 2018-09-10T08:18:33Z | - |
dc.date.available | 2018-09-10T08:18:33Z | - |
dc.date.issued | 2010-04 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/359369 | - |
dc.description.abstract | Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions g1, ?, gn, i.e., f = h(g1, ?, gn). It plays an important role in many aspects of electronic design automation (EDA). Prior approaches to the exploration of functional dependency are based on binary decision diagrams (BDDs), which may not be easily scalable to large designs. This paper formulates both single-output and multiple-output functional dependencies as satisfiability (SAT) solving and exploits extensively the capability of a modern SAT solver. Thereby, functional dependency can be detected effectively through incremental SAT solving, and the dependency function h, if it exists, is obtained through Craig interpolation. The proposed method enables 1) scalable detection of functional dependency, 2) fast enumeration of dependency function under a large set of candidate base functions, and 3) potential application to large-scale logic synthesis and formal verification. Experimental results show that the proposed method is far superior to prior work and scales well in dealing with the largest ISCAS and ITC benchmark circuits with up to 200K gates. ? 2010 IEEE. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE Transactions on Computers (TCOMP) | en_US |
dc.source | AH-anncc | - |
dc.subject | Automatic synthesis; Design aids; Logic design; Optimization. | - |
dc.subject.classification | [SDGs]SDG3 | - |
dc.subject.other | Automatic synthesis; Base function; Benchmark circuit; Craig interpolation; Electronic design automation; Formal verifications; Functional dependency; Large designs; Logic synthesis; Potential applications; SAT solvers; SAT-solving; Satisfiability; Boolean functions; Computer aided design; Decision theory; Logic design; Binary decision diagrams | - |
dc.title | To SAT or Not to SAT: Scalable Exploration of Functional Dependency | - |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TC.2010.12 | - |
dc.identifier.scopus | 2-s2.0-77649259348 | - |
dc.identifier.isi | WOS:000274794100003 | - |
dc.relation.pages | 457-467 | - |
dc.relation.journalvolume | 59 | - |
dc.relation.journalissue | 4 | - |
item.openairetype | journal article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Center for Artificial Intelligence and Advanced Robotics | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.orcid | 0000-0002-2279-4732 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系 |
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