https://scholars.lib.ntu.edu.tw/handle/123456789/359401| Title: | A broadband chip-level power-bus model feasible for power integrity chip-package co-design in high-speed memory circuits | Authors: | Chuang, Hao-Hsiang TZONG-LIN WU Hsu, Chih-Jung Hong, J. Yu, Chun-Huang Cheng, A. Ku, J. Wu, Tzong-Lin |
Issue Date: | Feb-2010 | Journal Volume: | 52 | Journal Issue: | 1 | Start page/Pages: | 235-239 | Source: | IEEE Transactions on Electromagnetic Compatibility | URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/359401 | DOI: | 10.1109/TEMC.2009.2035614 |
| Appears in Collections: | 電機工程學系 |
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