https://scholars.lib.ntu.edu.tw/handle/123456789/366440
標題: | A 40-GHz fast-locked all-digital phase-locked loop using a modified bang-bang algorithm | 作者: | Chao-Ching Hung SHEN-IUAN LIU |
關鍵字: | All digital; digitally controlled oscillator (DCO); fast locked; phase-locked loop (PLL) | 公開日期: | 六月-2011 | 卷: | 58 | 期: | 6 | 起(迄)頁: | 321-325 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metaloxidesemiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectively, at 40 GHz. The measured locked times are 1.3 ms and 15 μ without and with the modified bang-bang algorithm, respectively. © 2011 IEEE. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/366440 https://www.scopus.com/inward/record.uri?eid=2-s2.0-79960030507&doi=10.1109%2fTCSII.2011.2149610&partnerID=40&md5=7ea0da4e154556e5eb782895764f1f25 |
ISSN: | 15497747 | DOI: | 10.1109/tcsii.2011.2149610 | SDG/關鍵字: | Jitter; All digital; All digital phase locked loop; Digitally controlled oscillators; fast locked; Frequency tuning range; Peak-to-peak jitter; Phase Locked Loop (PLL); Root mean square jitter; Phase locked loops |
顯示於: | 電機工程學系 |
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