https://scholars.lib.ntu.edu.tw/handle/123456789/380152
標題: | Routability-driven placement for hierarchical mixed-size circuit designs | 作者: | Hsu, M.-K. Chen, Y.-F. Huang, C.-C. Chen, T.-C. Chang, Y.-W. YAO-WEN CHANG |
關鍵字: | Physical design; Placement; Routability | 公開日期: | 2013 | 來源出版物: | Design Automation Conference | 摘要: | A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability. To optimize wirelength and routability simultaneously during placement, a new analytical net-congestion-optimization technique is also proposed. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time). Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids [Placement and Routing] General Terms Algorithms, Performance. Copyright ? 2013 ACM. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-84879866335&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/380152 |
DOI: | 10.1145/2463209.2488921 | SDG/關鍵字: | Circuit designs; Design hierarchy; Mixed-size designs; Participating teams; Physical design; Placement; Placement and routing; Routability; Computer aided design; Optimization; Turnaround time; Placers |
顯示於: | 電子工程學研究所 |
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