Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
32
Journal Issue
4
Pages
644 - 652
Date Issued
2013-01
Author(s)
Y. C. Huang
M. H. Tsai
W. S. Ding
J. C. M. Li
M. T. Chang
M. H. Tsai
C. M. Tseng
H. C. Li
Type
journal article