https://scholars.lib.ntu.edu.tw/handle/123456789/387318
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Cheng, C.W. | en_US |
dc.contributor.author | Lin, Y.S. | en_US |
dc.contributor.author | SHAO-YI CHIEN | - |
dc.creator | Cheng, C.W.;Lin, Y.S.;Chien, S.Y. | - |
dc.date.accessioned | 2018-09-10T14:57:58Z | - |
dc.date.available | 2018-09-10T14:57:58Z | - |
dc.date.issued | 2014 | - |
dc.identifier.issn | 15206130 | - |
dc.identifier.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-84920277154&partnerID=MN8TOARS | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/387318 | - |
dc.description.abstract | Reconfigurable architectures grant many circuits more flexibility as well as more efficiency. By dynamically reconnecting the datapath between calculation units, we can optimize the performance of many designs. Inspired by some prior works, we proposed a new MIMD Streaming (MIMDS) execution scheme on the aid of reconfigurable design, featuring high efficient stream processing. In this work, we also take the locality of programs into account when designing our reconfigurable architecture. Therefore, we use the permutation network [1] as our reconfigurable path, which provides less but enough reconfigurability, leading to less area cost and less power consumption. In this paper, we will take a commercial processor, C54x from Texas Instrument [2], as example, as well as detail the modification from the baseline C54x to our proposed MIMDS architecture. We show that with the extra ALUs and efficient datapath, C54x with MIMDS feature has overall 63% less execution cycles and 45% less memory access at most. Compared with traditional C54x, our design has only 12% area overhead. Besides, if we consider only configurable network, our permutation network saves 85% area compared to fully reconfigurable datapath while supports sufficient reconfigurability. © 2014 IEEE. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | en_US |
dc.source | AH-Scopus to ORCID | - |
dc.subject | digital signal processor; explicit datagraph execution; permutation network; reconfigurable architecture | - |
dc.subject.other | Digital signal processors; Memory architecture; Network architecture; Signal processing; Silicon compounds; Configurable networks; explicit datagraph execution; Permutation network; Reconfigurability; Reconfigurable designs; Stream processing; Streaming execution; Texas Instruments; Reconfigurable architectures | - |
dc.title | Efficient reconfigurable architecture for MIMD streaming execution using permutation network | - |
dc.type | conference paper | en |
dc.identifier.doi | 10.1109/SiPS.2014.6986090 | - |
dc.identifier.scopus | 2-s2.0-84920277154 | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.openairetype | conference paper | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Intel-NTU Connected Context Computing Center | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-0634-6294 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: International Research Centers | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電子工程學研究所 |
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