https://scholars.lib.ntu.edu.tw/handle/123456789/394592
標題: | A subharmonically injection-locked PLL with calibrated injection pulsewidth | 作者: | Chih-Lu Wei Ting-Kuei Kuan SHEN-IUAN LIU |
公開日期: | 六月-2015 | 卷: | 62 | 期: | 6 | 起(迄)頁: | 548-552 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A subharmonically injection-locked phase-locked loop (SIPLL) using a pulsewidth-calibrated loop is presented. The injection timing and the pulsewidth of the injected pulse are calibrated to tolerate the process variations. This SIPLL is fabricated in a 40-nm CMOS process. The measured output frequency ranges from 0.4 to 1.6 GHz. Its power is 1.49 mW for a supply of 1.1 V at 1.6 GHz. The root-mean-square jitter is 2.29 ps. © 2015 IEEE. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/394592 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84930628288&doi=10.1109%2fTCSII.2015.2407753&partnerID=40&md5=6b1c9a70f96ea2eb923b5527fe53bd9a |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2015.2407753 | SDG/關鍵字: | Electrical engineering; Electronics engineering; Phase noise; Injection locked; Injection timing; Injection-locked phase-locked loop; Output frequency; Phase Locked Loop (PLL); Process Variation; Pulsewidths; Root mean square jitter; Phase locked loops Phase noise; phase-locked loop (PLL); pulsewidth-calibrated loop (PWCL); subharmonically injection locked |
顯示於: | 電機工程學系 |
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