An ultra-low-power dual-mode automatic sleep staging processor using neural-network-based decision tree
Journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Volume
66
Journal Issue
9
Pages
3504-3516
Date Issued
2019-09-01
Author(s)
Abstract
© 2004-2012 IEEE. This paper presents an ultra-low-power dual-mode automatic sleep staging processor design using a neural-network (NN)-based decision tree classifier to enable real-time, long-term, and flexible sleep monitoring. The ultra-low-power feature is achieved by an algorithm-hardware co-design approach that jointly considers optimization opportunities across the algorithm, architecture, and circuit levels to minimize power consumption; consequently, the first sub-10- μW NN-based automatic sleep staging processor is realized. The dual-mode NN models are trained by an open-source large-scale dataset. The default mode achieves 81.0% classification accuracy based on two signals of one electroencephalography (EEG) signal and one electromyography (EMG) signal, and the compact mode achieves 78.5% accuracy based on only one EEG signal. In addition, the proposed design was verified using the National Taiwan University Hospital (NTUH) dataset, for which 81.1% and 77.1% accuracy is achieved in the default and the compact modes, respectively. A prototype chip using a 180-nm CMOS process occupies a total area of 11.74 mm2 and operates at 10 KHz while consuming 4.96 μ at 1.2 V.
Subjects
Automatic sleep staging; classifier; CMOS VLSI design; decision tree; digital signal processing (DSP); hardware implementation; low power; neuron network
Other Subjects
Biomedical signal processing; Classifiers; CMOS integrated circuits; Decision trees; Digital signal processing; Electroencephalography; Electrophysiology; Integrated circuit design; Large dataset; Low power electronics; Sleep research; Digital signal processing (DSP); Hardware implementations; Low Power; Neuron networks; Sleep staging; VLSI design; Neural networks
Type
journal article