A 24-GHz high linearity down-conversion mixer in 90-nm CMOS
Journal
IEEE InternTechnologyational Symposium of Radio Frequency Integrated
Pages
226-228
Date Issued
2018
Author(s)
Abstract
A 24-GHz high linearity down-conversion mixer in 90-nm CMOS is presented in this paper. The mixer utilizes folded architecture, LC tank, distributed derivative superposition (DS) linearization technique to achieve high linearity with relatively low power. The mixer achieves 0 dBm IP_1\mathbfdB. The mixer provides-3 dB conversion gain and the IIP3 is 21 dBm with only 10-mW dc consumption.
SDGs
Type
conference paper