https://scholars.lib.ntu.edu.tw/handle/123456789/427690
標題: | Design and Implementation of Cost-Efficient Probabilistic-Based Noise-Tolerant VLSI Circuits | 作者: | I-Chyn Wey You-Gang Chen Chang-Hong Yu An-Yeu Wu Jie Chen AN-YEU(ANDY) WU 吳安宇 |
關鍵字: | Cost-effective hardware design; Markov random field (MRF); Master-and-slave MRF mapping; Noise-tolerant circuit; Probabilistically based circuit | 公開日期: | 2009 | 卷: | 56 | 期: | 11 | 起(迄)頁: | 1450-1454 | 來源出版物: | IEEE Transactions onCircuits and Systems Part-I: Regular Papers | 摘要: | As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF-CLA) was implemented using the 0.13-μm CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF-CLA can provide a 7.00× 10-5 bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS-CLA can only provide 8.84×10-3 BER. Because of high noise immunity, the master-and-slave MRF-CLA can operate under 0.25 V to tolerate noise interference with only 1.9 μW of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF-CLA design. © 2006 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/427690 | DOI: | 10.1109/TCSI.2009.2015648 | SDG/關鍵字: | Bit error rate; CMOS integrated circuits; Energy utilization; Integrated circuit design; Integrated circuit manufacture; Magnetorheological fluids; Mapping; Markov processes; Random errors; Signal to noise ratio; Timing circuits; VLSI circuits; Carry look-ahead adder; Circuit reliability; CMOS process technology; Cost-effective methods; Design and implementations; Hardware design; Markov Random Fields; Noise-Tolerant; Cost effectiveness |
顯示於: | 電機工程學系 |
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