Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
16
Journal Issue
12
Pages
1月20日
Date Issued
2008
Author(s)
Abstract
Along with the progress of advanced VLSI technology, noise issues in dynamic circuits have become an imperative design challenge. The twin-transistor design, is the current state-of-the-art design to enhance the noise immunity in dynamic CMOS circuits. To achieve the high noise-tolerant capability, in this paper, we propose a new isolated noise-tolerant (INT) technique which is a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit INT Manchester adder can achieve 1.66times average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio (SNR) environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18-mu m process.
SDGs
Type
journal article