A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration
Journal
IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Pages
84:1-84:7
Date Issued
0
Author(s)
Abstract
A time-interleaved 12-b SAR ADC, employing the proposed digital calibration with a delay-sampling technique to correct timing skew, achieves a 600-MHz sampling rate. The 600-Ms/s ADC has been fabricated in a 40-nm CMOS technology, improving SFDR from 55 dB to 71 dB for a 100-MHz input signal. The 4-way interleaved ADC achieves a 61-dB SNDR while dissipating 23 mW from a 0.9-V power supply.
SDGs
Type
conference paper