A 1.5-GHz Sub-Sampling Fractional-N PLL for Spread-Spectrum Clock Generator in 0.18-μm CMOS
Journal
IEEE A-SSCC
Date Issued
2017
Author(s)
Abstract
This paper presents a fractional-N sub-sampling phase-locked loop (SSPLL) for spread-spectrum clock generator. A digital-to-time converter (DTC) is adopted to facilitate a fractional-N SSPLL. A digital calibration scheme is employed to eliminate DTC gain error. With the calibration method enabled, the PLL is successfully locked and achieves 18.98-dB EMI reduction. This PLL was fabricated in a TSMC 0.18-pm CMOS technology. The core area is 0.467 mm 2 . The chip dissipates 11.1 mW from a 1.8-V supply voltage.
SDGs
Type
conference paper