A wideband 90-nm CMOS phase-locked loop with current mismatch calibration for spur reduction
Journal
Asia-Pacific Microwave Conference Proceedings
Journal Volume
2018-November
Pages
1504-1506
Date Issued
2019
Author(s)
Abstract
This paper presents a wideband low-spur phase-locked loop (PLL) in a standard 90-nm CMOS process. A simple but effective calibration technique is used to reduce the current mismatch of the charge-pump and achieve low reference spurs. The calibration is based on the successive-approximation- register (SAR) control in conjunction with the pulse-width scaling technique to enlarge the current mismatch for a better calibration resolution. The operation frequency range of the microwave PLL covers from 39.5 to 47.1 GHz. The measured phase noise and reference spurs are -92 dBc/Hz at 1-MHz offset and -57.63 dBc, respectively.
SDGs
Type
conference paper