Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Biomedical Electronics and Bioinformatics / 生醫電子與資訊學研究所
Design of low latency on-chip communication based on hybrid NoC architecture
Details
Design of low latency on-chip communication based on hybrid NoC architecture
Journal
Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010
Pages
257-260
Date Issued
2010
Author(s)
Tsai, K.-L.
Lai, F.
Pan, C.-Y.
Xiao, D.-S.
Tan, H.-J.
Lee, H.-C.
FEI-PEI LAI
DOI
10.1109/NEWCAS.2010.5603934
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/484429
URL
https://www.scopus.com/inward/record.uri?eid=2-s2.0-78349262258&doi=10.1109%2fNEWCAS.2010.5603934&partnerID=40&md5=cfa07192e367621f0c26328a6d7c6e0a
Type
conference paper