Distinguishable error detection method for network on chip
Journal
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
Pages
3733-3736
Date Issued
2010
Author(s)
Abstract
In modern Network-on-Chip (NoC) design, how to guarantee the data correctness from source IP to destination IP becomes an important issue. Error detection can be one of the solutions of this problem. In this paper, a distinguishable error detection method and the corresponding router are proposed to solve the data correctness problem. In the proposed method, the significant or critical data will be checked strictly while the other data will be checked slightly. Simulation results demonstrate that the proposed method not only provides an effective error detection scheme but also has better power-delay product than conventional technique. ©2010 IEEE.
Type
conference paper