A bist RAM architecture with parallel testing in a microprogram ROM
Journal
Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an
Journal Volume
16
Journal Issue
5
Pages
685-690
Date Issued
1993
Author(s)
Huang, J.-M.
Abstract
Abstract Symmetrically simple test patterns for parallel testing of row/column pattern?sensitive faults in RAMs are proposed in this paper. Based on the concept of the maximum leakage current among the RAM cells, the worst case testing becomes the critically efficient method for RAM testing. Due to the simplicity of generating test patterns, we can implement a BIST RAM with test procedures stored in a microprogram ROM to reduce the cost and time of testing. The test complexity of row/column pattern?sensitive faults is reduced to O(N) in an N bits RAM as compared with O(N3/ 2) of [1].
Type
journal article