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College of Electrical Engineering and Computer Science / 電機資訊學院
Computer Science and Information Engineering / 資訊工程學系
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture
Details
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture
Journal
Proceedings - Design Automation Conference
Journal Volume
05-09-June-2016
Date Issued
2016
Author(s)
Wang, P.-H.
Li, C.-H.
CHIA-LIN YANG
DOI
10.1145/2897937.2898036
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/487730
URL
https://www.scopus.com/inward/record.uri?eid=2-s2.0-84977100256&doi=10.1145%2f2897937.2898036&partnerID=40&md5=76a2e5790b8bb6ac475c0a99b0fe5429
Type
conference paper