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College of Electrical Engineering and Computer Science / 電機資訊學院
Computer Science and Information Engineering / 資訊工程學系
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
Details
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
Journal
IEEE Non-Volatile Memory System and Applications Symposium, NVMSA 2015, Hong Kong, China, August 19-21, 2015
Pages
1-6
Date Issued
2015
Author(s)
Lin, Ye-Jyun
Yang, Chia-Lin
Li, Hsiang-Pang
CHIA-LIN YANG
DOI
10.1109/NVMSA.2015.7304363
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/487757
URL
https://doi.org/10.1109/NVMSA.2015.7304363
Type
conference paper