Design space exploration for deterministic ethernet-based architecture of automotive systems.
Journal
IEEE International High Level Design Validation and Test Workshop, HLDVT 2016, Santa Cruz, CA, USA, October 7-8, 2016
Pages
53-61
Date Issued
2016
Author(s)
Joshi, Prachi
G.
Vedahari Narasimhan
Zeng, Haibo
Shukla, Sandeep K.
Lin, Chung-Wei
Yu, Huafeng
Abstract
Time Triggered Ethernet (TTE) is a time-triggered network technology with large bandwidth and services for deterministic, safety-relevant communication. Hence, it has gained increasing attention from domains such as aerospace, automotive and industrial applications. In this work, we aim to solve the problem of task mapping and communication scheduling in automotive design. The system model is a dataflow task communication model mapped to a target architecture based on TIE. The design variables are the mapping of tasks onto the end systems in the architecture and the scheduling of all frames. The constraints include the schedulability of tasks and signals, as well as the latency constraints of the critical paths as specified by the designer. It can be shown that the problem is NP· hard. Therefore, we develop a heuristic to solve this problem. The heuristic contains four steps and all of them (except scheduling) are formulated using Integer Linear Programming (ILP). We present experimental results on an industrial benchmark and two synthetic benchmarks which show the efficiency and scalability of our approach.
SDGs
Type
conference paper