A 1.5 bit 5th order CT/DT delta sigma class D amplifier with power efficiency improvement.
Journal
International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA
Pages
280-283
Date Issued
2008
Author(s)
Abstract
This paper describes the design and implementation of a 1.5 bit 5 th order CT/DT delta sigma class D amplifier. This chip integrated a 1.5 bit delta sigma modulator and full bridge power stages with programmable dead time control circuits. With the proposed 1.5 bit delta sigma modulator and dead time calibration techniques, 0.02% THD+N ratio, 16 dB dynamic range and 8% power efficiency improvement are achieved in a 0.35 um polycide CMOS technology. This chip consumes 7.8 mA and works at 3 V to 5.5 V supply range. The die area is 6 mm 2 .
SDGs
Type
conference paper