Performance comparison of flip-chip-assembled 5-GHz 0.18-μm CMOS power amplifiers on different packaging substrates
Journal
IEEE Transactions on Components, Packaging and Manufacturing Technology
Journal Volume
3
Journal Issue
12
Pages
2014-2021
Date Issued
2013
Author(s)
Abstract
In this paper, three 5-GHz power amplifiers (PAs) are presented, which were implemented in 0.18-μm CMOS technology on different package substrates using flip-chip assembly. To make a fair comparison, the three PAs use the same circuit topology and transistor peripherals. The first case is a fully on-chip integrated CMOS PA with on-chip inductors. The second case uses low-temperature cofired ceramic (LTCC) inductors for the matching network, and the CMOS die is flip-chip-assembled on the LTCC substrate. For the last case, the CMOS bare die is assembled on the ceramic integrated passive device (CIPD) substrate, also by the flip-chip technique, and CIPD inductors are used as the matching network. Moreover, the PA performances with respect to the quality factor of inductors are discussed and verified with the experimental results. The fully on-chip integrated CMOS PA performs at 25.2 dB gain and 22.5 dBm OP\rm SAT with a peak PAE of 22%. The system-in-package (SiP) CMOS PA on LTCC demonstrates 27 dB gain and 23.5 dBm OP\rm SAT with a peak PAE of 27.5%, and the SiP CMOS PA on CIPD performs with 26.8 dB gain and 24 dBm of OP \rm SAT with a peak PAE of 30%. With low-loss inductors on LTCC or CIPD, the maximum improvements of gain and PAE at P\rm SAT can be up to 1.5 dB and 8 percentage Points, compared to the fully on-chip PA. To our knowledge, this is the first comprehensive PA performance comparison for different SiP approaches. © 2013 IEEE.
Type
journal article