https://scholars.lib.ntu.edu.tw/handle/123456789/497779
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jiang, J.-H. | en_US |
dc.contributor.author | Jou, J.-Y. | en_US |
dc.contributor.author | Huang, J.-D. | en_US |
dc.contributor.author | JIE-HONG JIANG | zz |
dc.creator | Jiang, J.-H.;Jou, J.-Y.;Huang, J.-D. | - |
dc.date.accessioned | 2020-06-11T06:11:13Z | - |
dc.date.available | 2020-06-11T06:11:13Z | - |
dc.date.issued | 2001 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/497779 | - |
dc.relation.ispartof | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | - |
dc.title | Unified functional decomposition via encoding for FPGA technology mapping | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/92.924031 | - |
dc.identifier.scopus | 2-s2.0-0035301376 | - |
dc.identifier.url | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0035301376&doi=10.1109%2f92.924031&partnerID=40&md5=adbc073673178ad1a0dfb6abadd58618 | - |
dc.relation.pages | 251-260 | - |
dc.relation.journalvolume | 9 | - |
dc.relation.journalissue | 2 | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.openairetype | journal article | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.orcid | 0000-0002-2279-4732 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系 |
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