Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits.

Please use this identifier to cite or link to this item: https://scholars.lib.ntu.edu.tw/handle/123456789/497781

Title:	Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits.
Authors:	Chang, Yi-Fan Evan Huang, Ruei-Yang Jiang, Jie-Hong R. JIE-HONG JIANG
Issue Date:	2019
Start page/Pages:	19-26
Source:	25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019
URI:	https://scholars.lib.ntu.edu.tw/handle/123456789/497781
DOI:	10.1109/ASYNC.2019.00011
Appears in Collections:	電機工程學系

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