Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.

Journal

IEEE Trans. on CAD of Integrated Circuits and Systems

Journal Volume

19

Journal Issue

9

Pages

999-1010

Date Issued

2000

Author(s)

Jiang, Iris Hui-Ru

Chang, Yao-Wen

DOI

10.1109/43.863640

URI

https://scholars.lib.ntu.edu.tw/handle/123456789/497890

URL

https://doi.org/10.1109/43.863640

Type

journal article