ITimerC: Common path pessimism removal using effective reduction methods
Journal
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Journal Volume
2015-January
Journal Issue
January
Pages
600-605
Date Issued
2015
Author(s)
Abstract
Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis. To avoid exhaustive exploration on all paths in a design, in this paper, we present a novel timing analysis framework removing common path pessimism based on block-based static timing analysis, timing graph reduction, and dynamic bounding. Experimental results show that the proposed method is highly scalable, especially with short runtimes for large-scale designs. Moreover, our approach outperforms TAU 2014 timing contest winners, generating accurate results and achieving more than 2.13X speedups.
SDGs
Type
conference paper