Power-state-aware buffered tree construction
Journal
26th IEEE International Conference on Computer Design 2008, ICCD
Pages
21-26
Date Issued
2008
Author(s)
Abstract
Interconnect delay and low power are two of the main issues in nano technology. Buffer insertion during routing effectively reduces interconnect delay; power state management and multiple supply voltage significantly lower power consumption. However, buffering without considering power states in multiple supply voltage designs may cause the signal integrity problem. This paper first considers power states into buffered tree construction. Based on a hierarchical approach combined with dynamic programming, we can simultaneously minimize power, satisfy timing constraints and maintain signal integrity.
SDGs
Type
conference paper