https://scholars.lib.ntu.edu.tw/handle/123456789/497913
Title: | Timing Macro Modeling for Efficient Hierarchical Timing Analysis. | Authors: | Jiang, Iris Hui-Ru Lee, Pei-Yu HUI-RU JIANG |
Issue Date: | 2018 | Start page/Pages: | 714 | Source: | 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018 | URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/497913 | DOI: | 10.1109/ISVLSI.2018.00134 |
Appears in Collections: | 電機工程學系 |
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