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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Performance constraints aware voltage Islands generation in SoC floorplan design
Details
Performance constraints aware voltage Islands generation in SoC floorplan design
Journal
2006 IEEE International Systems-on-Chip Conference, SOC
Pages
211-214
Date Issued
2007
Author(s)
Lu, M.-C.
Wu, M.-C.
Chen, H.-M.
HUI-RU JIANG
DOI
10.1109/SOCC.2006.283883
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/497915
URL
https://www.scopus.com/inward/record.uri?eid=2-s2.0-43749116417&doi=10.1109%2fSOCC.2006.283883&partnerID=40&md5=55211917b1a2748e36bed2308067d302
SDGs
[SDGs]SDG7
Type
conference paper