A built-in gain calibration technique for RF low-noise amplifiers
Journal
Proceedings of the IEEE VLSI Test Symposium
Date Issued
2014
Author(s)
Abstract
A built-in calibration technique for radio-frequency low-noise amplifiers (LNAs) is presented in this paper. By means of two fully-integrated amplitude detectors, two transimpedance amplifiers (TIAs), a successive approximation register (SAR) controller, and a digital-to-analog converter (DAC), the gain of a LNA can be calibrated precisely by programming the ratio of on-chip resistance. By using a standard 0.18-μm CMOS process, a 5.2-GHz LNA with the proposed calibration loop is implemented. Based on the experimental results, 3-bit gain calibration is demonstrated with a gain error less than 1 dB. The fabricated LNA with the calibration scheme consumes a total de current of 12.4 mA from a 1.8-V supply.
SDGs
Type
conference paper