40Gb/S high-gain distributed amplifiers with cascaded gain stages in 0.18μm CMOS
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages
538-539+537+620
Date Issued
2007
Author(s)
Abstract
High-gain distributed amplifiers (DA) using cascaded stages as distributed cells are implemented in 0.18μm CMOS technology. Two DAs with 3×3 and 2×4 configurations are demonstrated for 40Gb/s applications. While consuming 250mW from a 2.8V supply, a GBW of up to 394GHz is achieved. ©2007 IEEE.
SDGs
Type
conference paper