A 10-Gb/s Inductorless CMOS Limiting Amplifier with Third-Order Interleaving Active Feedback
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
42
Journal Issue
5
Pages
1111-1120
Date Issued
2007
Author(s)
Abstract
This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-μm CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 231 -1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10 -12 are 300 and 10 mVPP, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68 × 0.8 mm2 where the active circuit area only occupies 0.32 × 0.6 mm2. © 2007 IEEE.
Subjects
Active feedback; Bandwidth enhancement techniques; Broadband amplifiers; Gain flatness; Inductive peaking; Limiting amplifiers; Optical communications
Other Subjects
Active feedback; Chip size; Inductive peaking; Input sensitivity; Bandwidth; Bit error rate; CMOS integrated circuits; Electric potential; Feedback; Gain control; Optical communication; Broadband amplifiers
Type
conference paper