Ultra-low-voltage CMOS static frequency divider
Journal
2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Pages
209-212
Date Issued
2006
Author(s)
Abstract
This paper presents an ultra-low-voltage static frequency divider fabricated in a standard 0.18-mum CMOS technology. Employing forward body-biasing (FBB) technique and parallel current switching topology, the 2:1 frequency divider operates up to 4.5 GHz while consuming 2.7 mW from a supply voltage of 0.6 V. When operating at a supply voltage of 0.7 V, a maximum operating frequency of 6.6 GHz is achieved at the cost of higher power dissipation
SDGs
Type
conference paper