Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications
Journal
Technical Digest - International Electron Devices Meeting, IEDM
Journal Volume
2018-December
Pages
21.4.1-21.4.4
Date Issued
2019
Author(s)
Sung, P.-J.
Chang, C.-Y.
Chen, L.-Y.
Kao, K.-H.
Su, C.-J.
Liao, T.-H.
Fang, C.-C.
Wang, C.-J.
Hong, T.-C.
Jao, C.-Y.
Hsu, H.-S.
Luo, S.-X.
Wang, Y.-S.
Huang, H.-F.
Li, J.-H.
Huang, Y.-C.
Hsueh, F.-K.
Wu, C.-T.
Huang, Y.-M.
Hou, F.-J.
Luo, G.-L.
Huang, Y.-C.
Shen, Y.-L.
Ma, W.C.-Y.
Huang, K.-P.
Lin, K.-L.
Samukawa, S.
Li, Y.
Huang, G.-W.
Lee, Y.-J.
Li, J.-Y.
Wu, W.-F.
Shieh, J.-M.
Chao, T.-S.
Yeh, W.-K.
Wang, Y.-H.
Abstract
For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 °C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.
Type
conference paper