https://scholars.lib.ntu.edu.tw/handle/123456789/498476
標題: | A low-jitter 8-to-10GHz distributed DLL for multiple-phase clock generation | 作者: | Hsiao, K.-J. TAI-CHENG LEE |
公開日期: | 2008 | 卷: | 51 | 起(迄)頁: | 513-515 | 來源出版物: | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 摘要: | We demonstrate a distributed DLL with low jitter and high phase accuracy for multiphase clock generation. The frequency of operation ranges from 8 to 10GHz. The measured RMS jitter is 293.3fs and the maximum phase mismatch is 1.4ps. The distributed DLL occupies 0.03mm2 active area in a 90nm CMOS technology and draws 15mA from a 1.0V supply. ©2008 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/498476 https://www.scopus.com/inward/record.uri?eid=2-s2.0-49549103575&doi=10.1109%2fISSCC.2008.4523283&partnerID=40&md5=0c1a91c2c8863d4e78b4ea006204f59f |
ISSN: | 01936530 | DOI: | 10.1109/ISSCC.2008.4523283 | SDG/關鍵字: | Clocks; Jitter; 90-nm cmos; Active area; Frequency of operation; Low jitters; Maximum phase; Multiphase clock; Phase accuracy; Phase clocks; Delay lock loops |
顯示於: | 電機工程學系 |
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