A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Journal Volume
53
Pages
300-301
Date Issued
2010
Author(s)
Huang, Y.-C.
Abstract
A 10 b pipelined ADC employs opamp and time-sharing techniques to reduce the power consumption and silicon area. The presented ADC needs only one opamp to complete the 10 b conversion. The chip is fabricated in a 90 nm digital CMOS process and occupies 0.058 mm 2 . It operates at 100 MS/S and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0 V supply.
SDGs
Type
conference paper