A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Journal Volume
57
Pages
362-363
Date Issued
2014
Author(s)
Abstract
Recently, dividerless PLL architectures, including sub-sampling PLLs [1] and injection-locked PLLs [2], have been reported to achieve superior phase noise with respect to conventional PLL architectures. However, these dividerless architectures can only be operated in integer-N mode inherently. In order to operate in fractional-N mode, this work proposes a digital pulse-width modulator (DPWM) to modulate the pulse width of the input reference signal to synthesize the output frequency.
Type
conference paper