A 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based MDLL
Journal
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages
C132-C133
Date Issued
2017
Author(s)
Abstract
An LC-VCO-based MDLL is presented in a fractional-N frequency synthesizer to extend its frequency multiplication factor and performance. By employing the proposed MUXs in the LC-VCO, it increases the loop bandwidth (BW) from 3MHz to 15MHz (nearly 0.4fREF) as well as flicker noise suppression. Moreover, the re-quantized delta-sigma modulator (DSM) is combined with the prototype in order to reduce spurious tones and in-band noise, which come from the gain error of the digital-to-time converter (DTC). Fabricated in a 40 nm CMOS technology, the proposed MDLL with a large frequency multiplication factor of 128 exhibits an integrated jitter of 177fs (integer-N) and 326fs (fractional-N) with power consumption of 1.81mW and 2.38mW from a 0.9V supply at 5.12GHz respectively. The FoMj of the proposed MDLL can be as good as -252.5dB (integer-N) and -246dB (fractional-N) with a reference frequency of 40MHz.
SDGs
Type
conference paper