New CMOS four-quadrant multiplier and squarer circuits
Journal
Analog Integrated Circuits and Signal Processing
Journal Volume
9
Journal Issue
3
Pages
257-263
Date Issued
1996
Author(s)
Abstract
A CMOS four-quadrant multiplier and a squarer using the positive feedback loops consisting of the current mirrors are presented. Simulation results are given to verify the theoretical analysis. The input range of this multiplier is over ±2.5V with the linearity error less than 1% and its -3dB bandwidth is about 20MHz. The total harmonic distortion is less than 1% with the input range up to ±2V The squarer has a ±1.6V input range. Second order effects such as mobility reduction and transistor mismatch have been discussed. Experimental results by using discrete components are also given. The proposed circuits are expected to be useful in analog signal-processing applications. © 1996 Kluwer Academic Publishers.
Type
journal article